AMD Moves 256-Core EPYC From Servers Into Embedded Systems

AMD announced the AMD EPYC Embedded 9006 Series SP7 on November 10, 2026. The lineup ranges from 64 to 256 cores, with the 128-core SKU scheduled to become available on November 15, 2026 and the remaining SKUs expected to begin shipping by the end of 2026. This is a separate embedded family from the 6th Gen EPYC 9006 server series launched in July 2026.

Image: AMD

What does AMD EPYC Embedded 9006 bring?

According to AMD, the series is built on the Zen 6 core architecture and supports up to 512 threads. The company also says it builds on the EPYC 9006 server CPU architecture, so the embedded chips descend from the 6th Gen EPYC (Venice) design without being the same product line. AMD claims up to 1.8x throughput, up to 1.5x higher I/O bandwidth, and up to 2.7x higher memory bandwidth versus the prior generation. Those figures come from AMD internal estimates and AMD testing, not independent benchmarks.

The 1.8x throughput claim is an internal SPECrate 2017_int_base estimate for a two-socket EPYC Embedded setup, not a guarantee that a single 256-core chip is 1.8x faster by itself. The I/O and memory bandwidth comparisons are internal estimates for the 128-core EPYC Embedded 9756 against published specifications for 5th Gen EPYC 9005 processors. The full footnotes are in AMD's Newsroom announcement.

The platform has 16 DDR5 memory channels, with RDIMM speeds up to 8,000 MT/s and MRDIMM speeds up to 12,800 MT/s. It also offers up to 96 PCIe Gen 6 lanes at 64 GT/s, flexible PCIe Gen 6 and CXL 3.1 connectivity, seven-year product longevity, and embedded-focused firmware and software support.

Which workloads is it designed for?

AMD is aiming the series at semiconductor automated test equipment (ATE), enterprise storage, and high-end 400G/800G network firewalls. Salil Raje, senior vice president and general manager of AMD's Adaptive and Embedded Computing Group, said, "As AI infrastructure grows, the systems that test semiconductors, secure networks and manage enterprise data must keep pace or risk becoming bottlenecks to progress." He added that the company is bringing data center-class compute to embedded systems and helping customers do more within their power budgets.

For firewalls, AMD cites up to 1.3x higher firewall throughput from a DPDK L3FWD test in October 2026, comparing the 128-core EPYC Embedded 9756 with the previous-generation 9755. For storage, it cites up to a 1.5x gain on an ISA-L benchmark; those system configurations also used different memory setups. The 9756 is the 128-core SKU. The 256-core figure is the top of the series range.

What security layers are included?

AMD describes three dedicated security engines. AMD root of trust (ART) establishes the silicon root of trust and secure boot, and supports post-quantum cryptography for firmware signing. The AMD Security Processor (ASP) orchestrates boot, provides runtime security and a trusted execution environment, and manages the keys used to protect virtual-machine memory. Caliptra, an open-source vendor-agnostic silicon root of trust, is used for device identity and attestation so a remote party can check that a device is genuine and that the expected BIOS and firmware are running.

Samsung, Lanner, Portwell, and IEI Integration also appear in the announcement. Lanner is positioning its NCA-6145 network appliance on the new CPUs. YT Lee, vice president at IEI Integration, said 96 lanes at 64 GT/s from a single socket let one test system validate large numbers of PCIe Gen 6 SSDs in parallel, at full speed. Samsung's quote also mentions a CXL 3.2 memory module, which should not be read as AMD's own CXL 3.1 feature set.

Feature	AMD EPYC Embedded 9006 Series SP7
Core range	64 to 256
Maximum threads	512
Memory	16 DDR5 channels, RDIMM 8,000 MT/s, MRDIMM 12,800 MT/s
I/O	Up to 96 PCIe Gen 6 lanes at 64 GT/s, plus CXL 3.1
Product longevity	7 years
First SKU	128-core, November 15, 2026

The embedded family should not be treated as the same launch as the server-focused 6th Gen EPYC 9006 chips. AMD's recent accelerator work also includes the Umbra quantum error-correction announcement.